Semiconductor large scale integrated circuits (simply, LSI in the following) are shipped after the phases of design, manufacturing and test. Here, test means the operation of determining whether products are defective or defect free by applying test vectors (hereinafter called simply as ‘vectors’ in the following) to LSI (concretely, the combinational circuit in a sequential circuit, that is, the circuit composed of logic elements of AND gate, NAND gate, OR gate, NOR gate, and so on) manufactured based on design data and by comparing the response with expected value. The rate of defect free LSI products which pass the test (yield) is the to be the key of semiconductor industry because the quality, reliability and cost of LSI depends on it greatly. And at-speed testing conducts tests of LSI at the operating speed of actual use. When vectors are composed of initialization pattern and of launch pattern which detect faults, as shown in FIG. 3, at-speed testing is conducted as follows. The initialization pattern is applied to a combinational circuit at the rising timing of a shift pulse SL. Subsequently, the launch pattern is applied to the combinational circuit at the rising timing of a pulse C1. And the resulted response of the combinational circuit is observed at the rising timing of a pulse C2. The testing state of the combinational circuit is finished at the rising timing of a shift pulse S1.
High launch-induced switching activity in a combinational circuit caused by applying the launch pattern after the pulse C1 results in frequent decrease of power supply voltage (IR-drop) and increase of power supply noise, increasing the delay in the combinational circuit. If the delay increases too much, the adequate response which should be obtained at the timing of the pulse C2 cannot be obtained, resulting in capturing a wrong response to flip-flops in the sequential circuit by timing error. Consequently, test malfunction where a product is wrongly determined as defective occurs because the response from the combinational circuit doesn't match the expected value. And test malfunctions occur frequently in at-speed testing where the timing gap between capture C1 and capture C2 is narrow.
There is a method for generating a vector which doesn't cause IR-drop, called X-filling technique. When detecting one or a plurality of kinds of faults to be detected in an LSI (concretely, the combinational circuit in a sequential circuit), it is possible to detect the faults by assigning logic values 0 or 1 only to a part of bits which relates to detecting the faults in the vector. X-filling technique is a technique to determine the rest of the bits which don't relate to detecting the faults (that is, which don't decrease fault coverage) in the vector as unspecified bits (X-bits) and to assign logic values 0 or 1 to the X-bits for a particular purpose. For example, when the response Fp(V) and Fs(V) are obtained for a vector V which is composed of Vp and Vs, as shown in FIG. 4, the difference can be decreased between Vs and Fs(V). Here, in the FIG. 4, pi (i=1 to 6) and qi (i=1 to 6) denotes input lines and output lines of the combinational circuit 11, respectively. In Patent Document 1, X-bit identification from any bit for the whole vector set is described.
Patent Document 1: WO 2006/106626 A1.